1. Field of the Invention
The present invention relates to electronic devices, and in particular, to select signal circuits for low voltage swing circuits.
2. Description of Related Art
Low-voltage-swing (LVS) circuits have been developed as a means to decrease circuit area, increase throughput and consume less power than other circuit families. LVS circuits utilize large networks of pre-charged dual rail gates with low voltage outputs and sense amplifiers to restore the output to full rail signals. In contrast to full-voltage swing circuits, a low-voltage-swing logic circuit may provide valid data output signals based on a relatively small difference in potential between a pair of complementary data input signals. More specifically, a first data wire is used to carry a true value of the valid data signal and a second data wire is used to carry a complementary value of the same valid data signal. In a two-phase clocking arrangement, during a first clocking or pre-charging phase, both the data wires are pre-charged to a predetermined or pre-charge potential. At this point, the data wires do not contain any valid data or information. During a second clocking or evaluating phase, the potentials on the two wires may diverge in response to the information content of an input data signal. In particular, one data wire “evaluates” by transitioning toward an evaluation potential and the second data wire remains at the pre-charge potential, the low-voltage-swing logic arrangement then provides a valid data output signal based on the potential or voltage difference between the valid true and complementary data input signals. After the second clocking or evaluating phase, both data wires are again pre-charged to their pre-charge potential during a succeeding first clocking or pre-charge phase.
With respect to inputs to precharged-low LVS circuits, many circuit branches may drive the same LVS node. In these topologies the select logic of the LVS circuit is such that during LVS evaluation phase, only one of these branches will drive the LVS node. Even though logically only one branch can be selected, it is possible that a branch selected during the previous cycle's evaluation phase is still turning OFF when the LVS circuit enters the current evaluation phase. This phenomenon can create potential differential in the direction opposite to the proper logical value. In such a case, this phenomenon slows down the operation of the LVS circuit. The reason for this is that the reverse differential (differential noise) must first be overcome before a differential can be built up in the correct direction. If a pulsed clock system is used to clock the LVS circuit and the contention period is significant, then the LVS circuit may not be able to overcome the reverse differential and a functional failure of an integrated circuit (e.g. a microprocessor) containing the LVS circuit may occur.
Reverse differential build-up can be avoided by using precharged-low dynamic selects as an input to the LVS circuit. In this case the domino logic providing the dynamic selects needs to be in phase with the LVS circuit. However, a dynamic select is not a viable solution if the LVS circuit is distributed over a large distance, because in this case the LVS select maximum and minimum timing window is non-existent (negative) for sufficiently fast target frequencies. Furthermore, a dynamic signal distributed across a long distance is susceptible to pulse evaporation if the clock period is sufficiently short (high target frequency). Therefore, the use of static selects signals to enable a distributed LVS circuit is sometimes unavoidable.
FIG. 1 illustrates the current state of the art for generating static LVS select signals for an illustrative LVS circuit 10, while minimizing or eliminating reverse differential build-up in the LVS circuit 10. A generic, master-slave flip-flop 12 drives the select signals with a minimum number of stages to the LVS circuit 10. The LVS circuit 10 may be a distributed structure; therefore, the LVS select signal may have to span a long distance. The illustrative LVS circuit 10, in this case, is shown as a 3:1 multiplexer circuit. The driving flip-flop 12 is triggered a phase ahead of the evaluation phase of the LVS circuit 10. In this example the select signals SA, SB, and SC are applied to the LVS circuit 10. These select signals are mutually exclusive signals and therefore logically only one of the three signals will be HIGH during the evaluation phase of the LVS circuit 10. The rising of the flip-flop clock signal (CLOCK1) triggers the flip-flop 12 and the select signal that was HIGH in the previous cycle transitions from HIGH to LOW, while another select signal for the current evaluation period transitions from LOW to HIGH. Ensuring that the turning-OFF edge of the previous select signal occurs before the LVS circuit 10 begins its next evaluation eliminates reverse differential build-up in the LVS circuit 10. In order to speedup the data-dependant turning-OFF edge, the number of buffer stages 16 between the flip-flop 12 and LVS circuit 10 has been minimized to one.
The prior art circuit arrangement of FIG. 1 illustrates the best-known method to eliminate reverse differential build-up, which is to speed up the turning-OFF edge of the select signals such that the LVS branch that is ON from the previous evaluation cycle is OFF before the next LVS evaluation phase begins. This is achieved by: (A) minimizing the number of buffer stages between the master-slave flip-flop 12 driving the select signals and the LVS circuit 10; (B) skewing the buffer stages 16 between the flip-flop 12 and the LVS circuit 10 such that the turning OFF edge is sped up at the expense of the turning ON edge; and (C) speeding up the clock signal to the flip-flop 12 such that the flip-flop 12 is triggered earlier in order to speedup the arrival times of the select signal's de-assertion and assertion edges at the gate inputs of the LVS circuit 10.
The master-slave flip-flop 12 includes a master and a slave latch, with each having an open and a close state. The latches pass through the data when in the open state and hold (latch) the data when in the close state. When the master latch in the close state is holding the data acquired from the previous clock phase, the slave latch in the open state is passing the data being held by the master latch through to the flip-flop's output. When the clock phase is reversed, the master latch switches to its open state to acquire new data and at the same time the slave latch switches from its open state of acquiring the master latch's output data to its close state of holding the previous-provided data. Hence, the master and slave latches operate “out-of-phase”.